SemiAnalysis is reporting breaking news that NVIDIA has open sourced parts of its Rubin NVSwitch tray design, including a Bill of Materials (BoM) and technical diagrams. The announcement is framed as a significant transparency move for people who study, build, and validate advanced data-center systems, because it provides more than just high-level descriptions.
At the center of the report is the “NVSwitch tray” associated with NVIDIA’s Rubin platform. NVSwitch is a key part of the system interconnect architecture, used to enable high-bandwidth, low-latency communication between GPUs inside a rack. For many researchers and engineers, understanding exactly how these components are arranged—and what supporting compute elements are included—matters as much as the headline GPU specifications.
According to the SemiAnalysis summary, NVIDIA’s open-sourced materials include both a BoM and diagrams for the NVSwitch tray. A BoM is especially valuable because it enumerates the actual components used in the tray design. Diagrams help clarify how the parts connect and how the overall system is laid out physically and logically. Together, these resources can allow ecosystem partners, hardware integrators, and knowledgeable observers to better interpret the design intent and evaluate how the system is expected to behave.
The report further states that the open-sourced tray design explicitly includes an AMD EPYC 3151 embedded CPU. This detail is notable for a few reasons. First, it provides a concrete confirmation that at least some control or management workload in the NVSwitch tray is intended to run on an AMD embedded processor rather than purely relying on other components. Second, it helps demystify the “supporting silicon” that often goes unmentioned in marketing material. While GPUs handle the bulk compute and NVSwitch handles the GPU-to-GPU traffic, the tray still needs coordination, monitoring, firmware services, and system-level control. The inclusion of the EPYC 3151 suggests that NVIDIA is using a standard embedded server-class CPU to perform those roles.
The SemiAnalysis write-up also ties the tray design into the larger rack configuration. It notes that there are 9 NVSwitch trays per VR200 rack. If NVIDIA’s tray design is replicated across all nine trays in a rack, then the number of tray-level embedded CPUs scales accordingly.
Based on that system-level mapping, SemiAnalysis highlights that this results in an estimate of 9 small AMD embedded CPUs per NVIDIA rack (one EPYC 3151 per tray, multiplied by nine trays). This kind of arithmetic may sound straightforward, but the implication is important: when buyers and evaluators consider operational characteristics such as management-plane performance, reliability strategy, power budgeting, and failure domains, they need to understand what additional compute devices exist beyond the GPUs.
While the report focuses on open sourcing and the revealed component list, it also implicitly speaks to a broader trend in the industry: greater hardware documentation and openness around complex system design. For advanced infrastructure, being able to see a BoM and diagrams can help the community validate assumptions, perform reverse engineering more systematically, and potentially support verification and integration work.
There are also practical reasons why the EPYC 3151 detail matters. An embedded CPU within the tray likely participates in tasks such as coordinating NVSwitch operation, managing telemetry, orchestrating configuration, and handling local control functions. Even if most of the performance-critical workload is elsewhere, the control plane still impacts stability and manageability. Knowing the exact CPU model gives analysts a clearer picture of what software stack might be involved and what capabilities—such as networking, I/O options, and firmware characteristics—are available.
In short, SemiAnalysis presents NVIDIA’s open-sourced NVSwitch tray BoM and diagrams as a meaningful technical disclosure. The most eye-catching element is the confirmed use of an AMD EPYC 3151 embedded CPU in the tray design, which—when combined with the cited “9 trays per VR200 rack” detail—yields an estimated 9 embedded AMD CPUs per rack.
Source: SemiAnalysis
SemiAnalysis: BREAKING NEWS: NVIDIA HAS JUST OPEN SOURCED THEIR RUBIN NVSWITCH TRAY BoM & DIAGRAM & IT INCLUDES AMD EYPC 3151 EMBEDDED CPU. Since there is 9 NVSwitch Trays Per VR200 Rack, that is 9 small AMD embedded CPUs per NVIDIA rack. NVIDIA has open sourced this in their. #breaking
— @SemiAnalysis_ May 1, 2026
SHOP AMAZON BEST SELLERS, CLICK TO BUY FROM AMAZON.
SHOP AMAZON BEST SELLERS, CLICK TO BUY FROM AMAZON.
